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lt6220/lt6221/lt6222 1 622012fa C + i pd photodiode ~4pf v s + v s + v s + v s C v s C lt6220 100k 3.24k 33k 10k 1pf 30pf lt1634-1.25 v out v s = 1.5v to 5v 622012 ta01 low voltage, high frequency signal processing driving a/d converters rail-to-rail buffer amplifiers active filters video amplifiers fast current sensing amplifiers gain bandwidth product: 60mhz input common mode range includes both rails output swings rail-to-rail low quiescent current: 1ma max input offset voltage: 350 v max input bias current: 150na max wide supply range: 2.2v to 12.6v large output current: 50ma typ low voltage noise: 10nv hz typ slew rate: 20v/ s typ common mode rejection: 102db typ power supply rejection: 105db typ open-loop gain: 100v/mv typ operating temperature range: C 40 c to 85 c single in the 8-pin so and 5-pin low profile (1mm) thinsot tm packages dual in the 8-pin so and (3mm x 3mm) dfn packages quad in the 16-pin ssop package single/dual/quad 60mhz, 20v/ s, low power, rail-to-rail input and output precision op amps the lt ? 6220/lt6221/lt6222 are single/dual/quad, low power, high speed rail-to-rail input and output operational amplifiers with excellent dc performance. the lt6220/ lt6221/lt6222 feature reduced supply current, lower input offset voltage, lower input bias current and higher dc gain than other devices with comparable bandwidth. typically, the lt6220/lt6221/lt6222 have an input off- set voltage of less than 100 v, an input bias current of less than 15na and an open-loop gain of 100v/mv. the parts have an input range that includes both supply rails and an output that swings within 10mv of either supply rail to maxi- mize the signal dynamic range in low supply applications. the lt6220/lt6221/lt6222 maintain performance for supplies from 2.2v to 12.6v and are specified at 3v, 5v and 5v supplies. the inputs can be driven beyond the supplies without damage or phase reversal of the output. the lt6220 is housed in the 8-pin so package with the standard op amp pinout as well as the 5-pin sot-23 package. the lt6221 is available in 8-pin so and dfn (3mm 3mm low profile dual fine pitch leadless) pack- ages with the standard op amp pinout. the lt6222 fea- tures the standard quad op amp configuration and is available in the 16-pin ssop package. the lt6220/ lt6221/ lt6222 can be used as plug-in replacements for many op amps to improve input/output range and performance. , ltc and lt are registered trademarks of linear technology corporation. stepped-gain photodiode amplifier features descriptio u applicatio s u typical applicatio u thinsot is a trademark of linear technology corporation. v os distribution, v cm = 0v (s8, pnp stage) input offset voltage ( v) C250 percent of units (%) 30 40 50 150 622012 g01 20 10 25 35 45 15 5 0 C150 C50 0 50 250 v s = 5v, 0v v cm = 0v
lt6220/lt6221/lt6222 2 622012fa total supply voltage (v s C to v s + ) ......................... 12.6v input voltage (note 2) .............................................. v s input current (note 2) ........................................ 10ma output short circuit duration (note 3) ............ indefinite operating temperature range (note 4) ...C40 c to 85 c specified temperature range (note 5) ....C40 c to 85 c order part number dd part* marking t jmax = 125 c, ja = 160 c/w (note 10) exposed pad internally connected to v s C (pcb connection optional) lt6221cdd lt6221idd absolute axi u rati gs w ww u package/order i for atio uu w (note 1) consult ltc marketing for parts specified with wider operating temperature ranges. *the temperature grades are identified by a label on the shipping container. maximum junction temperature .......................... 150 c (dd package) ................................................... 125 c storage temperature .............................C65 c to 150 c (dd package) ....................................C65 c to 125 c lead temperature (soldering, 10 sec.)................. 300 c top view dd package 8-lead (3mm 3mm) plastic dfn 5 6 7 8 4 3 2 1 out a Cin a +in a v s C v s + out b Cin b +in b a b top view gn package 16-lead narrow plastic ssop 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 out a Cin a +in a v s + +in b Cin b out b nc out d Cin d +in d v s C +in c Cin c out c nc a b c d t jmax = 150 c, ja = 135 c/w t jmax = 150 c, ja = 190 c/w order part number s8 part marking order part number ssop part marking lt6221cs8 lt6221is8 lt6222cgn lt6222ign ladz 6222 6222i 6221 6221i order part number order part number s5 part* marking s8 part marking t jmax = 150 c, ja = 190 c/w t jmax = 150 c, ja = 250 c/w (note 10) 1 2 3 4 8 7 6 5 top view nc Cin +in v s C nc v s + v out nc s8 package 8-lead plastic so + C 5 v s + 4 Cin v out 1 top view s5 package 5-lead plastic tsot-23 v s C 2 +in 3 + C lt6220cs8 lt6220is8 6220 6220i lt6220cs5 lt6220is5 ltafp 1 2 3 4 8 7 6 5 top view out a Cin a +in a v s C v s + out b Cin b +in b s8 package 8-lead plastic so a b
lt6220/lt6221/lt6222 3 622012fa electrical characteristics symbol parameter conditions min typ max units v os input offset voltage v cm = 0v 70 350 v v cm = 0v (dd package) 150 700 v v cm = 0v (s5 package) 200 850 v v cm = v s 0.5 2.5 mv v cm = v s (s5 package) 0.5 3 mv ? v os input offset voltage shift v s = 5v, v cm = 0v to 3.5v 30 195 v v s = 3v, v cm = 0v to 1.5v 15 120 v input offset voltage match (channel-to-channel) v cm = 0v 100 600 v (note 9) v cm = 0v (dd package) 150 1100 v i b input bias current v cm = 1v 15 150 na v cm = v s 250 600 na input bias current match (channel-to-channel) v cm = 1v 15 175 na (note 9) v cm = v s 20 250 na i os input offset current v cm = 1v 15 100 na v cm = v s 15 100 na input noise voltage 0.1hz to 10hz 0.5 v p-p e n input noise voltage density f = 10khz 10 nv/ hz i n input noise current density f = 10khz 0.8 pa/ hz c in input capacitance 2pf a vol large signal voltage gain v s = 5v, v o = 0.5v to 4.5v, r l = 1k at v s /2 35 100 v/mv v s = 5v, v o = 1v to 4v, r l = 100 ? at v s /2 3.5 10 v/mv v s = 3v, v o = 0.5v to 2.5v, r l = 1k at v s /2 30 90 v/mv cmrr common mode rejection ratio v s = 5v, v cm = 0v to 3.5v 85 102 db v s = 3v, v cm = 0v to 1.5v 82 102 db cmrr match (channel-to-channel) (note 9) v s = 5v, v cm = 0v to 3.5v 79 100 db v s = 3v, v cm = 0v to 1.5v 76 100 db input common mode range 0 v s v psrr power supply rejection ratio v s = 2.5v to 10v, v cm = 0v 84 105 db psrr match (channel-to-channel) (note 9) 79 105 db minimum supply voltage (note 6) 2.2 2.5 v v ol output voltage swing low (note 7) no load 5 40 mv i sink = 5ma 100 200 mv i sink = 20ma 325 650 mv v oh output voltage swing high (note 7) no load 5 40 mv i source = 5ma 130 250 mv i source = 20ma 475 900 mv i sc short-circuit current v s = 5v 20 45 ma v s = 3v 20 35 ma i s supply current per amplifier 0.9 1 ma gbw gain-bandwidth product v s = 5v, frequency = 1mhz 35 60 mhz sr slew rate v s = 5v, a v = C1, r l = 1k, v o = 4v 10 20 v/ s fpbw full power bandwidth v s = 5v, a v = 1, v o = 4v p-p 1.6 mhz hd harmonic distortion v s = 5v, a v = 1, r l = 1k, v o = 2v p-p , f c = 500khz C77.5 dbc t s settling time 0.01%, v s = 5v, v step = 2v, a v = 1, r l = 1k 300 ns ? g differential gain (ntsc) v s = 5v, a v = 2, r l = 1k 0.3 % ? differential phase (ntsc) v s = 5v, a v = 2, r l = 1k 0.3 deg t a = 25 c, v s = 5v, 0v; v s = 3v, 0v; v cm = v out = half supply, unless otherwise noted
lt6220/lt6221/lt6222 4 622012fa symbol parameter conditions min typ max units v os input offset voltage v cm = 0v 90 500 v v cm = 0v (dd package) 180 850 v v cm = 0v (s5 package) 230 1250 v v cm = v s 0.5 3 mv v cm = v s (s5 package) 0.5 3.5 mv ? v os input offset voltage shift v s = 5v, v cm = 0v to 3.5v 30 280 v v s = 3v, v cm = 0v to 1.5v 15 190 v input offset voltage match (channel-to-channel) v cm = 0v 110 850 v (note 9) v cm = 0v (dd package) 180 1400 v v os tc input offset voltage drift (note 8) 1.5 5 v/ c (s5 package) 3.5 10 v/ c i b input bias current v cm = 1v 20 175 na v cm = v s C 0.2v 275 800 na input bias current match (channel-to-channel) v cm = 1v 15 200 na (note 9) v cm = v s C 0.2v 20 300 na i os input offset current v cm = 1v 15 125 na v cm = v s C 0.2v 15 125 na a vol large signal voltage gain v s = 5v, v o = 0.5v to 4.5v, r l = 1k at v s /2 30 90 v/mv v s = 5v, v o = 1v to 4v, r l = 100 ? at v s /2 3 9 v/mv v s = 3v, v o = 0.5v to 2.5v, r l = 1k at v s /2 25 80 v/mv cmrr common mode rejection ratio v s = 5v, v cm = 0v to 3.5v 82 100 db v s = 3v, v cm = 0v to 1.5v 78 100 db cmrr match (channel-to-channel) (note 9) v s = 5v, v cm = 0v to 3.5v 77 100 db v s = 3v, v cm = 0v to 1.5v 73 100 db input common mode range 0v s v psrr power supply rejection ratio v s = 2.5v to 10v, v cm = 0v 81 104 db psrr match (channel-to-channel) (note 9) 76 104 db minimum supply voltage (note 6) 2.2 2.5 v v ol output voltage swing low (note 7) no load 850 mv i sink = 5ma 110 220 mv i sink = 20ma 375 750 mv v oh output voltage swing high (note 7) no load 850 mv i source = 5ma 150 300 mv i source = 20ma 600 1100 mv i sc short-circuit current v s = 5v 20 40 ma v s = 3v 20 30 ma i s supply current per amplifier 1 1.4 ma gbw gain-bandwidth product v s = 5v, frequency = 1mhz 30 60 mhz sr slew rate v s = 5v, a v = C1, r l = 1k, v o = 4v p-p 918 v/ s electrical characteristics the denotes the specifications which apply over the 0 c t a 70 c temperature range. v s = 5v, 0v; v s = 3v, 0v; v cm = v out = half supply, unless otherwise noted.
lt6220/lt6221/lt6222 5 622012fa symbol parameter conditions min typ max units v os input offset voltage v cm = 0v 125 700 v v cm = 0v (dd package) 300 1300 v v cm = 0v (s5 package) 350 2000 v v cm = v s 0.75 3.5 mv v cm = v s (s5 package) 1 4.5 mv ? v os input offset voltage shift v s = 5v, v cm = 0v to 3.5v 30 300 v v s = 3v, v cm = 0v to 1.5v 30 210 v input offset voltage match (channel-to-channel) v cm = 0v 175 1200 v (note 9) v cm = 0v (dd package) 300 2200 v v os tc input offset voltage drift (note 8) 1.5 7.5 v/ c (s5 package) 3.5 15 v/ c i b input bias current v cm = 1v 25 200 na v cm = v s C 0.2v 300 900 na input bias current match (channel-to-channel) v cm = 1v 15 250 na (note 9) v cm = v s C 0.2v 20 350 na i os input offset current v cm = 1v 20 150 na v cm = v s C 0.2v 20 150 na a vol large signal voltage gain v s = 5v, v o = 0.5v to 4.5v, r l = 1k at v s /2 25 70 v/mv v s = 5v, v o = 1.5v to 3.5v, r l = 100 ? at v s /2 2.5 8 v/mv v s = 3v, v o = 0.5v to 2.5v, r l = 1k at v s /2 20 60 v/mv cmrr common mode rejection ratio v s = 5v, v cm = 0v to 3.5v 81 100 db v s = 3v, v cm = 0v to 1.5v 77 100 db cmrr match (channel-to-channel) (note 9) v s = 5v, v cm = 0v to 3.5v 76 100 db v s = 3v, v cm = 0v to 1.5v 72 100 db input common mode range 0v s v psrr power supply rejection ratio v s = 2.5v to 10v, v cm = 0v 79 104 db psrr match (channel-to-channel) (note 9) 74 104 db minimum supply voltage (note 6) 2.2 2.5 v v ol output voltage swing low (note 7) no load 10 60 mv i sink = 5ma 120 240 mv i sink = 10ma 220 450 mv v oh output voltage swing high (note 7) no load 10 60 mv i source = 5ma 160 325 mv i source = 10ma 325 650 mv i sc short-circuit current v s = 5v 12.5 30 ma v s = 3v 12.5 25 ma i s supply current per amplifier 1.1 1.5 ma gbw gain-bandwidth product v s = 5v, frequency = 1mhz 25 50 mhz sr slew rate v s = 5v, a v = C1, r l = 1k, v o = 4v 815 v/ s electrical characteristics the denotes the specifications which apply over the 40 c t a 85 c temperature range. v s = 5v, 0v; v s = 3v, 0v; v cm = v out = half supply unless otherwise noted. (note 5)
lt6220/lt6221/lt6222 6 622012fa symbol parameter conditions min typ max units v os input offset voltage v cm = C5v 80 500 v v cm = C5v (dd package) 150 750 v v cm = C5v (s5 package) 200 900 v v cm = 5v 0.7 2.5 mv v cm = 5v (s5 package) 0.7 3 mv ? v os input offset voltage shift v cm = C5v to 3.5v 70 675 v input offset voltage match (channel-to-channel) v cm = C5v 100 850 v v cm = C5v ( dd package) 150 1300 v i b input bias current v cm = C4v 20 150 na v cm = 5v 250 700 na input bias current match (channel-to-channel) v cm = C4v 15 175 na v cm = 5v 20 250 na i os input offset current v cm = C4v 15 100 na v cm = 5v 15 100 na input noise voltage 0.1hz to 10hz 0.5 v p-p e n input noise voltage density f = 10khz 10 nv/ hz i n input noise current density f = 10khz 0.8 pa/ hz c in input capacitance f = 100khz 2 pf a vol large signal voltage gain v o = C 4v to 4v, r l = 1k 35 95 v/mv v o = C2v to 2v, r l = 100 ? 3.5 10 v/mv cmrr common mode rejection ratio v cm = C5v to 3.5v 82 102 db cmrr match (channel-to-channel) 77 100 db input common mode range v s C v s + v psrr power supply rejection ratio v s + = 2.5v to 10v, v s C = 0v, v cm = 0v 84 105 db psrr match (channel-to-channel) 79 105 db v ol output voltage swing low (note 7) no load 5 40 mv i sink = 5ma 100 200 mv i sink = 20ma 325 650 mv v oh output voltage swing high (note 7) no load 5 40 mv i source = 5ma 130 250 mv i source = 20ma 475 900 mv i sc short-circuit current 25 50 ma i s supply current per amplifier 1 1.5 ma gbw gain-bandwidth product frequency = 1mhz 60 mhz sr slew rate a v = C1, r l = 1k , v o = 4v, 20 v/ s measure at v o = 2v fpbw full power bandwidth v o = 8v p-p 0.8 mhz hd harmonic distortion a v = 1, r l = 1k, v o = 2v p-p , f c = 500khz C77.5 dbc t s settling time 0.01%, v step = 5v, a v = 1, r l = 1k 375 ns ? g differential gain (ntsc) a v = 2, r l = 1k 0.15 % ? differential phase (ntsc) a v = 2, r l = 1k 0.6 deg electrical characteristics t a = 25 c, v s = 5v, v cm = 0v, v out = 0v, unless otherwise noted.
lt6220/lt6221/lt6222 7 622012fa symbol parameter conditions min typ max units v os input offset voltage v cm = C5v 100 650 v v cm = C5v (dd package) 180 900 v v cm = C5v (s5 package) 230 1300 v v cm = 5v 0.75 3 mv v cm = 5v (s5 package) 0.75 3.5 mv ? v os input offset voltage shift v cm = C5v to 3.5v 90 850 v input offset voltage match (channel-to-channel) v cm = C5v 90 1100 v (note 9) v cm = C5v (dd package) 180 1500 v v os tc input offset voltage drift (note 8) 1.5 5 v/ c (s5 package) 3.5 10 v/ c i b input bias current v cm = C4v 20 175 na v cm = 4.8v 275 800 na input bias current match (channel-to-channel) v cm = C4v 15 200 na (note 9) v cm = 4.8v 20 300 na i os input offset current v cm = C4v 15 125 na v cm = 4.8v 15 125 na a vol large signal voltage gain v o = C 4v to 4v, r l = 1k 30 90 v/mv v o = C2v to 2v, r l =100 ? 3 9 v/mv cmrr common mode rejection ratio v cm = C5v to 3.5v 80 100 db cmrr match (channel-to-channel) (note 9) 75 100 db input common mode range v s C v s + v psrr power supply rejection ratio v s + = 2.5v to 10v, v s C = 0v, v cm = 0v 81 104 db psrr match (channel-to-channel) (note 9) 76 104 db v ol output voltage swing low (note 7) no load 850 mv i sink = 5ma 110 220 mv i sink = 20ma 375 750 mv v oh output voltage swing high (note 7) no load 850 mv i source = 5ma 150 300 mv i source = 20ma 600 1100 mv i sc short-circuit current 20 40 ma i s supply current per amplifier 1.2 2 ma gbw gain-bandwidth product frequency = 1mhz 60 mhz sr slew rate a v = C1, r l = 1k , v o = 4v, 18 v/ s measure at v o = 2v electrical characteristics the denotes the specifications which apply over the 0 c t a 70 c temperature range. v s = 5v, v cm = 0v, v out = 0v, unless otherwise noted.
lt6220/lt6221/lt6222 8 622012fa symbol parameter conditions min typ max units v os input offset voltage v cm = C5v 150 800 v v cm = C5v (dd package) 300 1300 v v cm = C5v (s5 package) 350 2000 v v cm = 5v 0.75 3.5 mv v cm = 5v (s5 package) 1 4.5 mv ? v os input offset voltage shift v cm = C 5v to 3.5v 90 950 v input offset voltage match (channel-to-channel) v cm = C5v 175 1350 v (note 9) v cm = C5v (dd package) 300 2200 v v os tc input offset voltage drift (note 8) 1.5 7.5 v/ c (s5 package) 3.5 15 v/ c i b input bias current v cm = C4v 25 200 na v cm = 4.8v 300 900 na input bias current match (channel-to-channel) v cm = C4v 15 250 na (note 9) v cm = 4.8v 20 350 na i os input offset current v cm = C4v 20 150 na v cm = 4.8v 20 150 na a vol large signal voltage gain v o = C4v to 4v, r l = 1k 25 70 v/mv v o = C1v to 1v, r l = 100 ? 2.5 8 v/mv cmrr common mode rejection ratio v cm = C5v to 3.5v 79 100 db cmrr match (channel-to-channel) (note 9) 74 100 db input common mode range C5 5 v psrr power supply rejection ratio v s + = 2.5v to 10v, v s C = 0v, v cm = 0v 79 104 db psrr match (channel-to-channel) (note 9) 74 104 db v ol output voltage swing low (note 7) no load 10 60 mv i sink = 5ma 120 240 mv i sink = 10ma 220 450 mv v oh output voltage swing high (note 7) no load 10 60 mv i source = 5ma 160 325 mv i source = 10ma 325 650 mv i sc short-circuit current 12.5 30 ma i s supply current 1.4 2.25 ma gbw gain-bandwidth product frequency = 1mhz 50 mhz sr slew rate a v = C1, r l = 1k, v o = 4v, 15 v/ s measure at v o = 2v note 1: absolute maximum ratings are those values beyond which the life of a device may be impaired. note 2: the inputs are protected by back-to-back diodes. if the differential input voltage exceeds 1.4v, the input current should be limited to less than 10ma. note 3: a heat sink may be required to keep the junction temperature below the absolute maximum rating when the output is shorted indefinitely. note 4: the lt6220c/lt6221c/lt6222c and lt6220i/lt6221i/lt6222i are guaranteed functional over the temperature range of C40 c and 85 c. note 5: the lt6220c/lt6221c/lt6222c are guaranteed to meet specified performance from 0 c to 70 c. the lt6220c/lt6221c/lt6222c are designed, characterized and expected to meet specified performance from C40 c to 85 c but is not tested or qa sampled at these temperatures. the lt6220i/lt6221i/lt6222i are guaranteed to meet specified performance from C40 c to 85 c. note 6: minimum supply voltage is guaranteed by power supply rejection ratio test. note 7: output voltage swings are measured between the output and power supply rails. note 8: this parameter is not 100% tested. note 9: matching parameters are the difference between amplifiers a and d and between b and c on the lt6222; between the two amplifiers on the lt6221. note 10: thermal resistance ( ja ) varies with the amount of pc board metal connected to the package. the specified values are for short traces connected to the leads. if desired, the thermal resistance can be substantially reduced by connecting pin 2 of the lt6220cs5/lt6220is5 or the underside metal of dd packages to a larger metal area (v s C trace). electrical characteristics the denotes the specifications which apply over the 40 c t a 85 c temperature range. v s = 5v, v cm = 0v, v out = 0v, unless otherwise noted. (note 5)
lt6220/lt6221/lt6222 9 622012fa typical perfor a ce characteristics uw v os distribution, v cm = 0v (s8, pnp stage) input offset voltage ( v) C250 percent of units (%) 30 40 50 150 622012 g01 20 10 25 35 45 15 5 0 C150 C50 0 50 250 v s = 5v, 0v v cm = 0v input offset voltage ( v) C1000 percent of units (%) 30 40 50 600 622012 g02 20 10 25 35 45 15 5 0 C600 C200 0 200 1000 v s = 5v, 0v v cm = 0v input offset voltage ( v) C2000 percent of units (%) 30 40 50 1200 622012 g03 20 10 25 35 45 15 5 0 C1200 C400 400 0 2000 v s = 5v, 0v v cm = 5v v os distribution, v cm = 0v (sot5, pnp stage) v os distribution, v cm = 5v (s8, npn stage) v os distribution, v cm = 5v (sot5, npn stage) supply current vs supply voltage offset voltage vs input common mode voltage input offset voltage ( v) C3000 percent of units (%) 30 40 50 1800 622012 g04 20 10 25 35 45 15 5 0 C1800 C600 0 600 3000 v s = 5v, 0v v cm = 5v total supply voltage (v) 0 0 supply current per amplifier (ma) 1 2 3 2 468 622012 g05 10 1 3 5 7 9 11 12 t a = 125 c t a = C55 c t a = 25 c input common mode voltage (v) 0 C700 offset voltage ( v) C500 C300 C100 700 300 1 2 500 100 3 4 5 622012 g06 v s = 5v, 0v typical part t a = C55 c t a = 125 c t a = 25 c input bias current vs common mode voltage input bias current vs temperature output saturation voltage vs load current (output low) common mode voltage (v) 0 input bias current (na) 0 200 400 4 622012 g07 C200 C400 C100 100 300 C300 C500 C600 1 2 3 5 6 v s = 5v, 0v t a = C55 c t a = 25 c t a = 125 c temperature ( c) C55 input bias current ( a) 0.3 0.4 0.5 125 622012 g08 0.1 C0.2 C25 5 35 65 95 0.6 0.2 0 C0.1 v s = 5v, 0v npn active v cm = 5v pnp active v cm = 1v load current (ma) 0.01 0.001 output saturation voltage (v) 0.1 10 110 0.1 100 622012 g09 0.01 1 v s = 5v, 0v t a = C55 c t a = 125 c t a = 25 c
lt6220/lt6221/lt6222 10 622012fa typical perfor a ce characteristics uw output saturation voltage vs load current (output high) minimum supply voltage output short-circuit current vs power supply voltage open-loop gain open-loop gain offset voltage vs output current warm-up drift vs time input noise voltage vs frequency load current (ma) 0.01 0.001 output saturation voltage (v) 0.1 10 110 0.1 100 622012 g10 0.01 1 v s = 5v, 0v t a = C55 c t a = 125 c t a = 25 c total supply voltage (v) C0.6 change in offset voltage (mv) C0.2 0.2 0.6 C0.4 0 0.4 1.5 2.5 3.5 4.5 622012 g11 5.5 1 02345 t a = C55 c t a = 125 c t a = 25 c power supply voltage ( v) 1.5 C70 output short-circuit current (ma) C50 C30 C10 70 30 2 3 3.5 5 50 10 C60 C40 C20 60 20 40 0 2.5 4 4.5 622012 g12 t a = C55 c t a = C55 c sinking sourcing t a = 125 c t a = 125 c t a = 25 c t a = 25 c output voltage (v) 0 C1000 change in offset voltage ( v) C600 C200 200 0.5 1 1.5 2 622012 g13 2.5 600 1000 C800 C400 0 400 800 3 r l = 1k v s = 3v, 0v r l to gnd r l = 100 ? output voltage (v) 0 change in offset voltage ( v) 200 600 1000 4 622012 g14 C200 C600 0 400 800 C400 C800 C1000 1 0.5 2 1.5 3 3.5 4.5 2.5 6 r l = 1k v s = 5v, 0v r l to gnd r l = 100 ? open-loop gain output voltage (v) C5 change in offset voltage ( v) 200 600 1000 3 622012 g15 C200 C600 0 400 800 C400 C800 C1000 C3 C4 C1 C2 12 4 0 5 r l = 1k v s = 5v r l to gnd r l = 100 ? output current (ma) C75 change in offset voltage (mv) 2.0 1.5 1.0 0.5 0 C0.5 C1.0 C1.5 C2.0 45 622012 g16 C45 C15 15 75 30 C60 C30 0 60 v s = 5v t a = C55 c t a = 125 c t a = 25 c time after power-up (seconds) 0 change in offset voltage ( v) 2 6 10 40 622012 g17 C2 C6 0 4 8 C4 C8 C10 10 5 20 15 30 35 45 25 50 lt6221 s8 v s = 2.5v lt6222 gn16 v s = 2.5v lt6220 sot5 v s = 2.5v lt6222 gn16 v s = 5v lt6220 sot5 v s = 5v lt6221 s8 v s = 5v frequency (khz) 10 noise voltage (nv/ hz) 20 25 35 40 0.01 1 10 100 622012 g18 0 0.1 30 15 5 v s = 5v, 0v npn active v cm = 4.25v pnp active v cm = 2.5v
lt6220/lt6221/lt6222 11 622012fa typical perfor a ce characteristics uw input current noise vs frequency 0.1hz to 10hz output voltage noise gain bandwidth and phase margin vs supply voltage frequency (khz) 1.0 noise current (pa/ hz) 2.0 3.0 0.5 1.5 2.5 0.01 1 10 100 622012 g19 0 0.1 v s = 5v, 0v npn active v cm = 4.25v pnp active v cm = 2.5v time (seconds) 0 output noise voltage (nv) 800 600 400 200 0 C200 C400 C600 C800 8 622012 g20 246 10 7 135 9 v s = 5v, 0v total supply voltage (v) 0 gain bandwidth (mhz) phase margin (deg) 50 70 90 8 622012 g21 60 80 20 40 60 70 30 50 2 1 4 3 67 9 5 10 phase margin gain bandwidth product t a = 25 c gain bandwidth and phase margin vs temperature temperature ( c) C55 gain bandwidth (mhz) phase margin (deg) 50 70 90 65 622012 g22 60 40 70 60 80 50 30 20 C25 5 35 95 125 v s = 2.5v v s = 2.5v gain bandwidth product phase margin v s = 5v v s = 5v frequency (hz) 10k 20 gain (db) phase (deg) 30 40 50 60 100k 1m 10m 100m 622012 g23 10 0 C10 C20 70 80 0 20 40 60 80 C20 C40 C60 C80 100 120 v s = 5v phase gain v s = 5v v s = 2.5v v s = 2.5v temperature ( c) C55 15 slew rate (v/ s) 20 25 30 C25 53565 622012 g24 95 125 a v = C1 r f = r g = 1k r l = 1k v s = 5v v s = 2.5v gain and phase vs frequency slew rate vs temperature gain vs frequency (a v = 1) output impedance vs frequency frequency (mhz) 0.1 C3 gain (db) 0 3 6 9 1 10 100 622012 g25 C6 C9 C12 C15 12 15 a v = 1 c l = 10pf r l = 1k v s = 5v v s = 2.5v gain vs frequency (a v = 2) frequency (mhz) 0.1 C3 gain (db) 0 3 6 9 1 10 100 622012 g26 C6 C9 C12 C15 12 15 a v = 2 r f = r g = 1k c f = 20pf c l = 10pf r l = 1k v s = 5v v s = 2.5v frequency (mhz) 0.01 0.1 output impedacne ( ? ) 10 1 0.1 1 10 620012 g27 0.001 1000 100 100 v s = 2.5v a v = 10 a v = 1 a v = 2
lt6220/lt6221/lt6222 12 622012fa typical perfor a ce characteristics uw common mode rejection ratio vs frequency power supply rejection ratio vs frequency series output resistor vs capacitive load frequency (mhz) 20 common mode rejection ratio (db) 40 60 80 100 0.01 1 10 100 622012 g28 0 0.1 120 v s = 5v, 0v frequency (mhz) 40 power supply rejection ratio (db) 80 120 20 60 100 0.001 0.1 1 10 100 622012 g29 0 0.01 v s = 5v, 0v positive supply negative supply capacitive load (pf) 10 20 overshoot (%) 25 30 35 40 100 1000 10000 622012 g31 15 10 5 0 45 50 v s = 5v, 0v a v = 1 r l = , unless noted r os = 10 ? r os = 20 ? r os = r l = 50 ? series output resistor vs capacitive load maximum undistorted output signal vs frequency 5v large-signal response capacitive load (pf) 10 20 overshoot (%) 25 30 35 40 100 1000 10000 622012 g32 15 10 5 0 45 50 r os = 10 ? r os = 20 ? r os = r l = 50 ? v s = 5v, 0v a v = 2 r l = , unless noted frequency (mhz) 2.0 output voltage swing (v p-p ) 3.0 3.5 4.5 5.0 0 0.1 1 10 622012 g35 1.0 0.01 4.0 2.5 1.5 v s = 5v, 0v r l = 1k a v = C1 a v = 2 1v/div 0v v s = 5v, 0v 100ns/div 622012 g36 a v = 1 r l = 1k 5v small-signal response 2.5v v s = 5v, 0v 50ns/div 622012 g37 a v = 1 r l = 1k 50mv/div frequency (mhz) 0.01 C70 distortion (dbc) C50 C30 0.1 1 10 622012 g33 C90 C80 C60 C40 C100 C110 v s = 5v, 0v a v = 1 v out = 2v p-p r l = 150 ? , 3rd r l = 150 ? , 2nd r l = 1k, 3rd r l = 1k, 2nd frequency (mhz) 0.01 C70 distortion (dbc) C50 C30 0.1 1 10 622012 g34 C90 C80 C60 C40 C100 C110 v s = 5v, 0v a v = 2 v out = 2v p-p r l = 150 ? , 3rd r l = 150 ? , 2nd r l = 1k, 3rd r l = 1k, 2nd distortion vs frequency distortion vs frequency
lt6220/lt6221/lt6222 13 622012fa typical perfor a ce characteristics uw 5v small-signal response output overdriven recovery 50mv/div 0v v s = 5v 50ns/div 622012 g39 a v = 1 r l = 1k v in 1v/div 0v v s = 5v, 0v 200ns/div 622012 g40 a v = 2 r l = 1k v out 2v/div 0v applicatio s i for atio wu uu q4 q18 q17 q16 q6 q3 q7 q1 q15 out q2 q11 q12 q9 q5 v bias i 1 d2 d1 d5 d4 d3 d6 d7 d8 esdd2 esdd1 +in Cin v C esdd3 esdd4 v + v + v C r2 r1 r3 r4 r5 622012 f01 + i 2 + i 3 c2 c c v C + c1 buffer and output bias v + v C q19 q14 q8 q13 q10 figure 1. lt6220/lt6221/lt6222 simplified schematic diagram circuit description the lt6220/lt6221/lt6222 have an input and output signal range that covers from the negative power supply to the positive power supply. figure 1 depicts a simplified schematic of the amplifier. the input stage comprises two differential amplifiers, a pnp stage, q1/q2, and an npn stage, q3/q4, that are active over different ranges of common mode input voltage. the pnp stage is active between the negative supply to approximately 1.2v below the positive supply. as the input voltage moves closer toward the positive supply, the transistor q5 will steer the tail current, i 1 , to the current mirror, q6/q7, activating the npn differential pair and the pnp pair becomes inactive for the rest of the input common mode range up to the positive supply. also, at the input stage, devices q17 to q19 act to cancel the bias current of the pnp input pair. when q1/q2 are active, the current in q16 is controlled to be the same as the current q1/q2. thus, the base current of q16 is nominally equal to the base current of the input devices. the base current of q16 is then mirrored by devices q17-q19 to cancel the base current of the input devices q1/q2. 5v large-signal response 0v v s = 5v 200ns/div 622012 g38 a v = 1 r l = 1k 2v/div
lt6220/lt6221/lt6222 14 622012fa a pair of complementary common emitter stages q14/q15 that enable the output to swing from rail-to-rail construct the output stage. the capacitors c2 and c3 form the local feedback loops that lower the output impedance at high frequency. these devices are fabricated by linear technologys proprietary high speed complementary bi- polar process. power dissipation the lt6222, with four amplifiers, is housed in a small 16-lead ssop package and typically has a thermal resis- tance ( ja ) of 135 c/w. it is necessary to ensure that the dies junction temperature does not exceed 150 c. the junction temperature, t j , is calculated from the ambient temperature, t a , power dissipation, p d , and thermal resis- tance, ja : t j = t a + (p d ? ja ) the power dissipation in the ic is the function of the supply voltage, output voltage and the load resistance. for a given supply voltage, the worst-case power dissipation p d(max) occurs when the maximum supply current and the output voltage is at half of either supply voltage for a given load resistance. p d(max) is given by: pvi v r d max s s max s l () () ?/ = () + ? ? ? ? ? ? 2 2 example: for an lt6222 in a 16-lead ssop package operating on 5v supplies and driving a 100 ? load, the worst-case power dissipation is given by: p amp ma mw dmax () /?../ .. . = () + () =+ = 10 1 8 2 5 100 0 018 0 0625 80 5 2 if all four amplifiers are loaded simultaneously, then the total power dissipation is 322mw. the maximum ambient temperature at which the part is allowed to operate is: t a = t j C (p d(max) ? 135 c/w) = 150 c C (0.322w ? 135 c/w) = 106.5 c applicatio s i for atio wu uu input offset voltage the offset voltage will change depending upon which input stage is active. the pnp input stage is active from the negative supply rail to 1.2v below the positive supply rail, then the npn input stage is activated for the remaining input range up to the positive supply rail during which the pnp stage remains inactive. the offset voltage is typically less than 70 v in the range that the pnp input stage is active. input bias current the lt6220/lt6221/lt6222 employ a patent pending technique to trim the input bias current to less than 150na for the input common mode voltage of 0.2v above the negative supply rail to 1.2v below the positive rail. the low input offset voltage and low input bias current of the lt6220/lt6221/lt6222 provide precision performance especially for high source impedance applications. output the lt6220/lt6221/lt6222 can deliver a large output current, so the short-circuit current limit is set around 50ma to prevent damage to the device. attention must be paid to keep the junction temperature of the ic below the absolute maximum rating of 150 c (refer to the power dissipation section) when the output is in continuous short circuit. the output of the amplifier has reverse- biased diodes connected to each supply. if the output is forced beyond either supply, unlimited current will flow through these diodes. if the current is transient and limited to several hundred milliamperes, no damage will occur to the device. overdrive protection when the input voltage exceeds the power supplies, two pair of crossing diodes, d1 to d4, will prevent the output from reversing polarity. if the input voltage exceeds either power supply by 700mv, diode d1/d2 or d3/d4 will turn on to keep the output at the proper polarity. for the phase reversal protection to perform properly, the input current must be limited to less than 5ma. if the amplifier is
lt6220/lt6221/lt6222 15 622012fa severely overdriven, an external resistor should be used to limit the overdriven current. the lt6220/lt6221/lt6222s input stages are also pro- tected against a large differential input voltage of 1.4v or higher by a pair of back-to-back diodes, d5/d8, to prevent the emitter-base breakdown of the input transistors. the current in these diodes should be limited to less than 10ma when they are active. the worse-case differential input voltage usually occurs when the input is driven while the output is shorted to ground in a unity-gain configura- tion. in addition, the amplifier is protected against esd strikes up to 3kv on all pins by a pair of protection diodes on each pin that are connected to the power supplies as shown in figure 1. capacitive load the lt6220/lt6221/lt6222 are optimized for high band- width, low power and precision applications. they can drive a capacitive load up to 100pf in a unity-gain configu- ration and more for higher gain. when driving a larger applicatio s i for atio wu uu capacitive load, a resistor of 10 ? to 50 ? should be connected between the output and the capacitive load to avoid ringing or oscillation. the feedback should still be taken from the output so that the resistor will isolate the capacitive load to ensure stability. graphs on capacitive loads show the transient response of the amplifier when driving capacitive load with specified series resistors. feedback components when feedback resistors are used to set up gain, care must be taken to ensure that the pole formed by the feedback resistors and the total capacitance at the inverting input does not degrade stability. for instance, the lt6220/ lt6221/lt6222, set up with a noninverting gain of 2, two 5k resistors and a capacitance of 5pf (part plus pc board), will probably oscillate. the pole is formed at 12.7mhz that will reduce phase margin by 52 degrees when the cross- over frequency of the amplifier is around 10mhz. a capaci- tor of 10pf or higher connecting across the feedback resistor will eliminate any ringing or oscillation. typical applicatio s u stepped-gain photodiode amplifier the circuit of figure 2 is a stepped gain transimpedance photodiode amplifier. at low signal levels, the circuit has a high 100k ? gain, but at high signal levels the circuit automatically and smoothly changes to a low 3.2k ? gain. the benefit of a stepped gain approach is that it maximizes dynamic range, which is very useful on limited supplies. put another way, in order to get 100k ? sensitivity and still handle a 1ma signal level without resorting to gain reduc- tion, the circuit would need a 100v negative voltage supply. the operation of the circuit is quite simple. at low photo- diode currents (below 10 a) the output and inverting input of the op amp will be no more than 1v below ground. the lt1634 in parallel with r3 and q2 keep a constant current though q2 of about 20 a. r4 maintains quiescent current through the lt1634 and pulls q2s emitter above ground, so q1 is reverse biased and no current flows through r2. so for small signals, the only feedback path is r1 (and c1) and the circuit is a simple transimpedance amplifier with 100k ? gain. figure 2. stepped-gain photodiode amplifier C + i pd photodiode ~4pf v s + v s + v s + v s C v s C lt6220 r1 100k r2 3.24k r3 33k r4 10k c1 1pf c2 30pf q1 q2 1 2 34 philips bcv62 lt1634-1.25 v out v s = 1.5v to 5v 622012 f02
lt6220/lt6221/lt6222 16 622012fa u package descriptio as the signal level increases though, the output of the op amp goes more negative. at 12.5 a of photodiode cur- rent, the 100k ? gain dictates that the lt6220 output will be about 1.25v below ground. however, at that point the emitter of q2 will be at ground, and the base of q1 will be 1v below ground. thus, q1 turns on and photodiode current starts to flow through r2. the transimpedance gain is therefore now reduced to r1||r2, or about 3.1k ? . the circuit response is shown in figure 3. note the smooth transition between the two operating gains, as well as the linearity. differential-in/differential-out amplifier the circuit of figure 6 shows the lt6222 applied as a buffered differential-in differential-out amplifier with a gain of 2. op amps a and b are configured as simple unity- gain buffers, offering high input impedance to upstream circuitry. resistors r1 and r2 perform an averaging function on the common mode input voltage and r3 attenuates it by a factor of 2/3 and references it to the voltage source v ocm . the resultant voltage, v mid = 2/3 ? v icm , is placed at the noninverting inputs of op amps c and d. the other four resistors set gains of +3 from the noninverting input and C2 through the inverting path. thus the output voltage of the upper path is: Cout = 3 ? (2/3 ? v icm + 1/3 ? v ocm ) C 2 ? (v icm + v diff /2) = 2v icm + v ocm C 2v icm C v diff = v ocm C v diff figure 4. 3v, 1mhz, 4th order butterworth filter figure 5. frequency response of filter figure 3. stepped-gain photodiode amplifier response photo current 100 a/div v out 0.5v/div 5 s/div 622012 f03 single 3v supply, 1mhz, 4th order butterworth filter the circuit shown in figure 4 makes use of the low voltage operation and the wide bandwidth of the lt6221 to create a dc accurate 1mhz 4th order lowpass filter powered from a 3v supply. the amplifiers are configured in the inverting mode for the lowest distortion and the output can swing rail-to-rail for maximum dynamic range. figure 5 displays the frequency response of the filter. stopband attenuation is greater than 100db at 50mhz. C + 1/2 lt6221 47pf 220pf v in v s /2 909 ? 2.67k 909 ? C + 1/2 lt6221 22pf v out 470pf 622012 f04 1.1k 2.21k 3v 1.1k frequency (hz) C80 gain (db) C40 0 C100 C60 C20 20 1k 100k 1m 10m 100m 622012 f05 C120 10k
lt6220/lt6221/lt6222 17 622012fa u package descriptio dd package 8-lead plastic dfn (3mm 3mm) (reference ltc dwg # 05-08-1698) u package descriptio and the output of the lower path is: +out = 3 ? (2/3 ? v icm + 1/3 ? v ocm ) C 2 ? (v icm C v diff /2) = 2v icm + v ocm C 2v icm + v diff = v ocm + v diff note that the input common mode voltage does not appear in the output as either a common mode or a difference mode term. however the voltage v ocm does appear in the output terms, and with the same polarity, so it sets up the output dc level. also, the differential input voltage v diff appears fully at both outputs with opposite polarity, giving rise to the effective differential gain of 2. calculations show that using 1% resistors gives worst-case input common mode feedthrough better than C31db, whether looking at the output common mode or difference mode. consider- ing the 6db of gain, worst-case common mode rejection ratio is 37db. (remember this is assuming 1% resistors. of course, this can be improved with more precise resis- tors.) results achieved on the bench with typical 1% resistors showed 67db of cmrr at low frequency and 40db cmrr at 1mhz. gains other than 2 can be achieved by setting r3 = ? (r1||r2), r5 = ? r4 and r7 = ? r6 where gain = . 3.00 0.10 (4 sides) note: 1. drawing to be made a jedec package outline m0-229 variation of (weed-1) 2. drawing not to scale 3. all dimensions are in millimeters 4. dimensions of exposed pad on bottom of package do not include mold flash. mold flash, if present, shall not exceed 0.15mm on any side 5. exposed pad shall be solder plated 6. shaded area is only a reference for pin 1 location on top and bottom of package 0.38 0.10 bottom viewexposed pad 1.65 0.10 (2 sides) 0.75 0.05 r = 0.115 typ 2.38 0.10 (2 sides) 1 4 8 5 pin 1 top mark (note 6) 0.200 ref 0.00 C 0.05 (dd8) dfn 1203 0.25 0.05 2.38 0.05 (2 sides) recommended solder pad pitch and dimensions 1.65 0.05 (2 sides) 2.15 0.05 0.50 bsc 0.675 0.05 3.5 0.05 package outline 0.25 0.05 0.50 bsc
lt6220/lt6221/lt6222 18 622012fa u package descriptio s5 package 5-lead plastic tsot-23 (reference ltc dwg # 05-08-1635) 1.50 C 1.75 (note 4) 2.80 bsc 0.30 C 0.45 typ 5 plcs (note 3) datum a 0.09 C 0.20 (note 3) s5 tsot-23 0302 pin one 2.90 bsc (note 4) 0.95 bsc 1.90 bsc 0.80 C 0.90 1.00 max 0.01 C 0.10 0.20 bsc 0.30 C 0.50 ref note: 1. dimensions are in millimeters 2. drawing not to scale 3. dimensions are inclusive of plating 3.85 max 0.62 max 0.95 ref recommended solder pad layout per ipc calculator 1.4 min 2.62 ref 1.22 ref 4. dimensions are exclusive of mold flash and metal burr 5. mold flash shall not exceed 0.254mm 6. jedec package reference is mo-193
lt6220/lt6221/lt6222 19 622012fa u package descriptio information furnished by linear technology corporation is believed to be accurate and reliable. however, no responsibility is assumed for its use. linear technology corporation makes no represen- tation that the interconnection of its circuits as described herein will not infringe on existing patent rights. gn package 16-lead plastic ssop (narrow .150 inch) (reference ltc dwg # 05-08-1641) gn16 (ssop) 0204 12 3 4 5 6 7 8 .229 C .244 (5.817 C 6.198) .150 C .157** (3.810 C 3.988) 16 15 14 13 .189 C .196* (4.801 C 4.978) 12 11 10 9 .016 C .050 (0.406 C 1.270) .015 .004 (0.38 0.10) 45 0 C 8 typ .007 C .0098 (0.178 C 0.249) .0532 C .0688 (1.35 C 1.75) .008 C .012 (0.203 C 0.305) typ .004 C .0098 (0.102 C 0.249) .0250 (0.635) bsc .009 (0.229) ref .254 min recommended solder pad layout .150 C .165 .0250 bsc .0165 .0015 .045 .005 *dimension does not include mold flash. mold flash shall not exceed 0.006" (0.152mm) per side **dimension does not include interlead flash. interlead flash shall not exceed 0.010" (0.254mm) per side inches (millimeters) note: 1. controlling dimension: inches 2. dimensions are in 3. drawing not to scale s8 package 8-lead plastic small outline (narrow .150 inch) (reference ltc dwg # 05-08-1610) .016 C .050 (0.406 C 1.270) .010 C .020 (0.254 C 0.508) 45 0 C 8 typ .008 C .010 (0.203 C 0.254) so8 0303 .053 C .069 (1.346 C 1.752) .014 C .019 (0.355 C 0.483) typ .004 C .010 (0.101 C 0.254) .050 (1.270) bsc 1 2 3 4 .150 C .157 (3.810 C 3.988) note 3 8 7 6 5 .189 C .197 (4.801 C 5.004) note 3 .228 C .244 (5.791 C 6.197) .245 min .160 .005 recommended solder pad layout .045 .005 .050 bsc .030 .005 typ inches (millimeters) note: 1. dimensions in 2. drawing not to scale 3. these dimensions do not include mold flash or protrusions. mold flash or protrusions shall not exceed .006" (0.15mm)
lt6220/lt6221/lt6222 20 622012fa linear technology corporation 1630 mccarthy blvd., milpitas, ca 95035-7417 (408) 432-1900 fax: (408) 434-0507 www.linear.com ? linear technology corporation 2003 lt/tp 0204 1k ?printed in usa related parts part number description comments lt1498/lt1499 dual/quad 10mhz, 6v/ s rail-to-rail input/ high dc accuracy, 475 v v os(max) max supply current 2.2ma/amp, output c load op amps wide supply range, 2.2v to 30v lt1800/lt1801/lt1802 single/dual/quad 80mhz, 25v/ s, 350 v v os(max) , 250na i bias(max) , max supply current 2ma/amp low power rail-to-rail input/output precision op amps lt1803/lt1804/lt1805 single/dual/quad 85mhz, 100v/ s 2mv v os(max) , max supply current 3ma/amp rail-to-rail input/output op amps lt1806/lt1807 single/dual 325mhz, 140v/ s rail-to-rail input/ high dc accuracy, 550 v v os(max) max low noise 3.5nv/ hz output op amps low distortion C 80dbc at 5mhz, power down (lt1806) lt1809/lt1810 single/dual 180mhz, rail-to-rail input/output op amps 350v/ s slew rate, low distortion C90dbc at 5mhz, power down (lt1809) u typical applicatio figure 6. buffered gain of 2 differential-in/differential-out amplifier C + a 1/4 lt6222 C + b 1/4 lt6222 C + d 1/4 lt6222 C + c 1/4 lt6222 r4 1k r6 1k v icm + v diff /2 +in v icm C v diff /2 Cin v s = 1.3v to 6v bw ? 11mhz r5 2k r7 2k 5.6pf 5.6pf r3 2k Cout +out 622012 f06 v ocm v s + v s C r1 2k v mid r2 2k

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